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Makefile Tutorial
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<h1>Makefiles</h1>
<h3>by example</h3>
<hr>
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Compiling your source code files can be tedious, specially when you want
 to include several source files and have to type the compiling command 
everytime you want to do it. <br>
Well, I have news for you... Your days of command line compiling are 
(mostly) over, because YOU will learn how to write Makefiles.<br>
Makefiles are special format files that together with the <i>make</i> utility will help you to automagically build and manage your projects.<br>
<p>
For this session you will need these files:<br>
</p><ul><li><a href="http://mrbook.org/tutorials/make/main.cpp">main.cpp</a></li>
<li><a href="http://mrbook.org/tutorials/make/hello.cpp">hello.cpp</a></li>
<li><a href="http://mrbook.org/tutorials/make/factorial.cpp">factorial.cpp</a></li>
<li><a href="http://mrbook.org/tutorials/make/functions.h">functions.h</a></li>
</ul>
I recommend creating a new directory and placing all the files in there.<p>
<i>note: I use g++ for compiling. You are free to change it to a compiler of your choice</i>
</p><h3>The make utility</h3>
If you run <pre>make</pre>this program will look for a file named <i>makefile</i> in your directory, and then execute it.<br>
If you have several makefiles, then you can execute them with the command:
<pre>make -f MyMakefile</pre>
There are several other switches to the <code>make</code> utility. For more info, <code>man make</code>.
<h3>Build Process</h3>
<ol>
<li>Compiler takes the source files and outputs object files</li>
<li>Linker takes the object files and creates an executable</li>
</ol>
<h3>Compiling by hand</h3>
The trivial way to compile the files and obtain an executable, is by running the command:
<pre>g++ main.cpp hello.cpp factorial.cpp -o hello
</pre>
<h3>The basic Makefile</h3>
The basic makefile is composed of:
<pre><i>
target: dependencies
[tab] system command
</i></pre>
This syntax applied to our example would look like:
<pre>all:
	g++ main.cpp hello.cpp factorial.cpp -o hello
</pre>
[Download <a href="http://mrbook.org/tutorials/make/Makefile-1">here</a>]<p>
To run this makefile on your files, type:</p><pre>make -f Makefile-1</pre>

On this first example we see that our target is called <i>all</i>. This is the default target for makefiles. The <i>make</i> utility will execute this target if no other one is specified.<br>
We also see that there are no dependencies for target <i>all</i>, so <i>make</i> safely executes the system commands specified.<br>
Finally, make compiles the program according to the command line we gave it.<br>

<h3>Using dependencies</h3>
Sometimes is useful to use different targets. This is because if you 
modify a single file in your project, you don't have to recompile 
everything, only what you modified. <br>
Here is an example:<br>
<pre>all: hello

hello: main.o factorial.o hello.o
	g++ main.o factorial.o hello.o -o hello

main.o: main.cpp
	g++ -c main.cpp

factorial.o: factorial.cpp
	g++ -c factorial.cpp

hello.o: hello.cpp
	g++ -c hello.cpp

clean:
	rm -rf *o hello

</pre>
[Download <a href="http://mrbook.org/tutorials/make/Makefile-2">here</a>]<p>
Now we see that the target <i>all</i> has only dependencies, but no system commands. In order for <i>make</i> to execute correctly, it has to meet all the dependencies of the called target (in this case <i>all</i>).<br>
Each of the dependencies are searched through all the targets available and executed if found.<br> 
In this example we see a target called <i>clean</i>. It is useful to have such target if you want to have a fast way to get rid of all the object files and executables.<br>

</p><h3>Using variables and comments</h3>
You can also use variables when writing Makefiles. It comes in handy in 
situations where you want to change the compiler, or the compiler 
options.
<pre># I am a comment, and I want to say that the variable CC will be
# the compiler to use.
CC=g++
# Hey!, I am comment number 2. I want to say that CFLAGS will be the
# options I'll pass to the compiler.
CFLAGS=-c -Wall

all: hello

hello: main.o factorial.o hello.o
	$(CC) main.o factorial.o hello.o -o hello

main.o: main.cpp
	$(CC) $(CFLAGS) main.cpp

factorial.o: factorial.cpp
	$(CC) $(CFLAGS) factorial.cpp

hello.o: hello.cpp
	$(CC) $(CFLAGS) hello.cpp

clean:
	rm -rf *o hello
</pre>
[Download <a href="http://mrbook.org/tutorials/make/Makefile-3">here</a>]<p>
As you can see, variables can be very useful sometimes. To use them, 
just assign a value to a variable before you start to write your 
targets. After that, you can just use them with the dereference operator
 $(VAR).
<br>
</p><h2>Where to go from here</h2>
With this brief introduction to Makefiles, you can create some very 
sophisticated mechanism for compiling your projects. However, this is 
just a tip of the iceberg. I don't expect anyone to fully understand the
 example presented below without having consulted some <a href="http://www.gnu.org/manual/make-3.79.1/html_node/make_toc.html">Make documentation</a> (which I had to do myself) or read pages 347 to 354 of your Unix book.<p> 
</p><pre>CC=g++
CFLAGS=-c -Wall
LDFLAGS=
SOURCES=main.cpp hello.cpp factorial.cpp
OBJECTS=$(SOURCES:.cpp=.o)
EXECUTABLE=hello

all: $(SOURCES) $(EXECUTABLE)
	
$(EXECUTABLE): $(OBJECTS) 
	$(CC) $(LDFLAGS) $(OBJECTS) -o $@

.cpp.o:
	$(CC) $(CFLAGS) $&lt; -o $@


</pre>
[Download <a href="http://mrbook.org/tutorials/make/Makefile-4">here</a>]<p>
If you understand this last example, you could adapt it to your own 
personal projects changing only 2 lines, no matter how many additional 
files you have !!!.</p><p>
</p><hr>
Hector Urtubia
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